PIC | xx | famille du composant, actuellement « 12, 14, 16, 17 et 18 ». | ||||||
---|---|---|---|---|---|---|---|---|
L | tolérance plus importante de la plage de tension | |||||||
XX | type de mémoire programme | |||||||
C | EPROM ou EEPROM | |||||||
CR | PROM | |||||||
F | Flash | |||||||
yy | Identificateur. | |||||||
zz | vitesse maximale du quartz de pilotage. |
Mem prog en octets | RAM en octets | EEPROM en octets | Fmax en MHz | E / S | Boîtier | |
12C508 | 512x12 | 25 | - | 4 | 6 | 8 broches |
---|---|---|---|---|---|---|
16C72A | 2048x14 | 128 | - | 20 | 22 | 28 broches |
16F84 | 1024x14 | 68 | 64 | 20 | 13 | 18 broches |
16F628 | 2028x14 | 224 | 128 | 20 | 16 | 18 broches |
16F876 | 8192x14 | 368 | 256 | 20 | 22 | 28 broches |
16F877 | 8192x14 | 368 | 256 | 20 | 33 | 40 broches |
Bank0 | 0x20-0x7F |
---|---|
Bank1 | 0xA0-0xFF |
Bank2 | 0x120-0x14F, 0x170-0x17F |
Bank3 | 0x1F0-0x1FF |
Bank | RP1 | RP0 |
---|---|---|
0 | 0 | 0 |
1 | 0 | 1 |
2 | 1 | 0 |
3 | 1 | 1 |
BSF STATUS, RP0 ;Bank 1 BCF STATUS, RP0 ;Return to Bank 0Le fichier de registre est organisé en 224 x 8 dans le PIC16F628A.
Banque0 | Banque1 | Banque2 | Banque3 | ||||
---|---|---|---|---|---|---|---|
Adr. | Nom | Adr. | Nom | Adr. | Nom | Adr. | Nom |
00h | Indirect addr. | 80h | Indirect addr. | 100h | Indirect addr. | 180h | Indirect addr. |
01h | TMR0 | 81h | OPTION_REG | 101h | TMR0 | 181h | OPTION_REG |
02h | PCL | 82h | PCL | 102h | PCL | 182h | PCL |
03h | STATUS | 83h | STATUS | 103h | STATUS | 183h | STATUS |
04h | FSR | 84h | FSR | 104h | FSR | 184h | FSR |
05h | PORTA | 86h | TRISA | 105h | -- | 185h | -- |
06h | PORTB | 86h | TRISB | 106h | PORTB | 186h | TRISB |
07h | -- | 87h | -- | 107h | -- | 187h | -- |
08h | -- | 88h | -- | 108h | -- | 188h | -- |
09h | -- | 89h | -- | 109h | -- | 189h | -- |
0Ah | PCLATH | 8Ah | PCLATH | 10Ah | PCLATH | 18Ah | PCLATH |
0Bh | INTCON | 8Bh | INTCON | 10Bh | INTCON | 18Bh | INTCON |
0Ch | PIR1 | 8Ch | PIE1 | 10Ch | -- | 18Ch | -- |
0Dh | -- | 8Dh | -- | 10Dh | -- | 18Dh | -- |
0Eh | TMR1L | 8Eh | PCON | 10Eh | -- | 18Eh | -- |
0Fh | TMR1H | 8Fh | -- | 10Fh | -- | 18Fh | -- |
10h | T1CON | 90h | -- | ||||
11h | TMR2 | 91h | -- | ||||
12h | T2CON | 92h | PR2 | ||||
13h | -- | 93h | -- | ||||
14h | -- | 94h | -- | ||||
15h | CCPR1L | 95h | -- | ||||
16h | CCPR1H | 96h | -- | ||||
17h | CCP1CON | 97h | -- | ||||
18h | RCSTA | 98h | TXSTA | ||||
19h | TXREG | 99h | SPBRG | ||||
1Ah | RCREG | 9Ah | EEDATA | ||||
1Bh | -- | 9Bh | EEADR | ||||
1Ch | -- | 9Ch | EECON1 | ||||
1Dh | -- | 9Dh | EECON2 | ||||
1Eh | -- | 9Eh | -- | ||||
1Fh | CMCON | 9Fh | VRCON | ||||
20h 6Fh | General Purpose Register 80 octets |
A0h EFh | General Purpose Register 80 octets | 120h 14Fh | General Purpose Register 48 octets | ||
150h 16Fh | -- | ||||||
70h - 7Fh | 16 octets | F0h - FFh | idem 70h-7fh | 170h - 17Fh | idem 70h-7fh | 1F0h - 1FFh | idem 70h-7fh |
BANK 0 | ||||||||||
---|---|---|---|---|---|---|---|---|---|---|
Address | Name | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 | Value on POR Reset(1) |
00h | INDF | Addressing this location uses contents of FSR to address data memory (not a physical register) | xxxx xxxx | |||||||
01h | TMR0 | Timer0 Module’s Register | xxxx xxxx | |||||||
02h | PCL | Program Counter’s (PC) Least Significant Byte | 0000 0000 | |||||||
03h | STATUS | IRP | RP1 | RP0 | TO | PD | Z | DC | C | 0001 1xxx |
04h | FSR | Indirect Data Memory Address Pointer | xxxx xxxx | |||||||
05h | PORTA | RA7 | RA6 | RA5 | RA4 | RA3 | RA2 | RA1 | RA0 | xxxx 0000 |
06h | PORTB | RB7 | RB6 | RB5 | RB4 | RB3 | RB2 | RB1 | RB0 | xxxx xxxx |
07h | — | Unimplemented | — | |||||||
08h | — | Unimplemented | — | |||||||
09h | — | Unimplemented | — | |||||||
0Ah | PCLATH | — | — | — | Write Buffer for upper 5 bits of Program Counter | ---0 0000 | ||||
0Bh | INTCON | GIE | PEIE | T0IE | INTE | RBIE | T0IF | INTF | RBIF | 0000 000x |
0Ch | PIR1 | EEIF | CMIF | RCIF | TXIF | — | CCP1IF | TMR2IF | TMR1IF | 0000-000 |
0Dh | — | Unimplemented | — | |||||||
0Eh | TMR1L | Holding Register for the Least Significant Byte of the 16-bit TMR1 Register | xxxx xxxx | |||||||
0Fh | TMR1H | Holding Register for the Most Significant Byte of the 16-bit TMR1 Register | xxxx xxxx | |||||||
10h | T1CON | — | — | T1CKPS1 | T1CKPS0 | T1OSCEN | T1SYNC | TMR1CS | TMR1ON | --00 0000 |
11h | TMR2 | TMR2 Module’s Register | 0000 0000 | |||||||
12h | T2CON | — | TOUTPS3 | TOUTPS2 | TOUTPS1 | TOUTPS0 | TMR2ON | T2CKPS1 | T2CKPS0 | -000 0000 |
13h | — | Unimplemented | — | |||||||
14h | — | Unimplemented | — | |||||||
15h | CCPR1L | Capture/Compare/PWM Register (LSB) | xxxx xxxx | |||||||
16h | CCPR1H | Capture/Compare/PWM Register (MSB) | xxxx xxxx | |||||||
17h | CCP1CON | — | — | CCP1X | CCP1Y | CCP1M3 | CCP1M2 | CCP1M1 | CCP1M0 | --00 0000 |
18h | RCSTA | SPEN | RX9 | SREN | CREN | ADEN | FERR | OERR | RX9D | 0000 000x |
19h | TXREG | USART Transmit Data Register | 0000 0000 | |||||||
1Ah | RCREG | USART Receive Data Register | 0000 0000 | |||||||
1Bh | — | Unimplemented | — | |||||||
1Ch | — | Unimplemented | — | |||||||
1Dh | — | Unimplemented | — | |||||||
1Eh | — | Unimplemented | — | |||||||
1Fh | CMCON | C2OUT | C1OUT | C2INV | C1INV | CIS | CM2 | CM1 | CM0 | 0000 0000 |
BANK 1 | ||||||||||
Address | Name | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 | Value on POR Reset(1) |
80h | INDF | Addressing this location uses contents of FSR to address data memory (not a physicalregister)xxxx xxxx | ||||||||
81h | OPTION | RBPU | INTEDG | T0CS | T0SE | PSA | PS2 | PS1 | PS0 | 1111 1111 |
82h | PCL | Program Counter’s (PC) Least Significant Byte | 0000 0000 | |||||||
83h | STATUS | IRP | RP1 | RP0 | TO | PD | Z | DC | C | 0001 1xxx |
84h | FSR | Indirect Data Memory Address Pointer | xxxx xxxx | |||||||
85h | TRISA | TRISA7 | TRISA6 | TRISA5 | TRISA4 | TRISA3 | TRISA2 | TRISA1 | TRISA0 | 1111 1111 |
86h | TRISB | TRISB7 | TRISB6 | TRISB5 | TRISB4 | TRISB3 | TRISB2 | TRISB1 | TRISB0 | 1111 1111 |
87h | — | Unimplemented | — | |||||||
88h | — | Unimplemented | — | |||||||
89h | — | Unimplemented | — | |||||||
8Ah | PCLATH | — | — | — | Write Buffer for upper 5 bits of Program Counter | ---0 0000 | ||||
8Bh | INTCON | GIE | PEIE | T0IE | INTE | RBIE | T0IF | INTF | RBIF | 0000 000x |
8Ch | PIE1 | EEIE | CMIE | RCIE | TXIE | — | CCP1IE | TMR2IE | TMR1IE | 0000-000 |
8Dh | — | Unimplemented | — | |||||||
8Eh | PCON | — | — | — | — | OSCF | — | POR | BOR | ---- 1-0x |
8Fh | — | Unimplemented | — | |||||||
90h | — | Unimplemented | — | |||||||
91h | — | Unimplemented | — | |||||||
92h | PR2 | Timer2 Period Register | 1111 1111 | |||||||
93h | — | Unimplemented | — | |||||||
94h | — | Unimplemented | — | |||||||
95h | — | Unimplemented | — | |||||||
96h | — | Unimplemented | — | |||||||
97h | — | Unimplemented | — | |||||||
98h | TXSTA | CSRC | TX9 | TXEN | SYNC | — | BRGH | TRMT | TX9D | 0000-010 |
99h | SPBRG | Baud Rate Generator Register | 0000 0000 | |||||||
9Ah | EEDATA | EEPROM Data Register | xxxx xxxx | |||||||
9Bh | EEADR | EEPROM Address Register | xxxx xxxx | |||||||
9Ch | EECON1 | — | — | — | — | WRERR | WREN | WR | RD | ---- x000 |
9Dh | EECON2 | EEPROM Control Register 2 (not a physical register) | ---- ---- | |||||||
9Eh | — | Unimplemented | — | |||||||
9Fh | VRCON | VREN | VROE | VRR | — | VR3 | VR2 | VR1 | VR0 | 000- 0000 |
BANK 2 | ||||||||||
Address | Name | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 | Value on POR Reset(1) |
100h | INDF | Addressing this location uses contents of FSR to address data memory (not a physical register) | xxxx xxxx | |||||||
101h | TMR0 | Timer0 Module’s Register | xxxx xxxx | |||||||
102h | PCL | Program Counter’s (PC) Least Significant Byte | 0000 0000 | |||||||
103h | STATUS | IRP | RP1 | RP0 | TO | PD | Z | DC | C | 0001 1xxx |
104h | FSR | Indirect Data Memory Address Pointer | xxxx xxxx | |||||||
105h | — | Unimplemented | — | |||||||
106h | PORTB | RB7 | RB6 | RB5 | RB4 | RB3 | RB2 | RB1 | RB0 | xxxx xxxx |
107h | — | Unimplemented | — | |||||||
108h | — | Unimplemented | — | |||||||
109h | — | Unimplemented | — | |||||||
10Ah | PCLATH | — | — | — | Write Buffer for upper 5 bits of Program Counter | ---0 0000 | ||||
10Bh | INTCON | GIE | PEIE | T0IE | INTE | RBIE | T0IF | INTF | RBIF | 0000 000x |
10Ch | — | Unimplemented | — | |||||||
10Dh | — | Unimplemented | — | |||||||
10Eh | — | Unimplemented | — | |||||||
10Fh | — | Unimplemented | — | |||||||
110h | — | Unimplemented | — | |||||||
111h | — | Unimplemented | — | |||||||
112h | — | Unimplemented | — | |||||||
113h | — | Unimplemented | — | |||||||
114h | — | Unimplemented | — | |||||||
115h | — | Unimplemented | — | |||||||
116h | — | Unimplemented | — | |||||||
117h | — | Unimplemented | — | |||||||
118h | — | Unimplemented | — | |||||||
119h | — | Unimplemented | — | |||||||
11Ah | — | Unimplemented | — | |||||||
11Bh | — | Unimplemented | — | |||||||
11Ch | — | Unimplemented | — | |||||||
11Dh | — | Unimplemented | — | |||||||
11Eh | — | Unimplemented | — | |||||||
11Fh | — | Unimplemented | — | |||||||
BANK 3 | ||||||||||
Address | Name | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 | Value on POR Reset(1) |
180h | INDF | Addressing this location uses contents of FSR to address data memory (not a physical register) | xxxx xxxx | |||||||
181h | OPTION | RBPU | INTEDG | T0CS | T0SE | PSA | PS2 | PS1 | PS0 | 1111 1111 |
182h | PCL | Program Counter’s (PC) Least Significant Byte | 0000 0000 | |||||||
183h | STATUS | IRP | RP1 | RP0 | TO | PD | Z | DC | C | 0001 1xxx |
184h | FSR | Indirect Data Memory Address Pointer | xxxx xxxx | |||||||
185h | — | Unimplemented | — | |||||||
186h | TRISB | TRISB7 | TRISB6 | TRISB5 | TRISB4 | TRISB3 | TRISB2 | TRISB1 | TRISB0 | 1111 1111 |
187h | — | Unimplemented | — | |||||||
188h | — | Unimplemented | — | |||||||
189h | — | Unimplemented | — | |||||||
18Ah | PCLATH | — | — | — | Write Buffer for upper 5 bits of Program Counter | ---0 0000 | ||||
18Bh | INTCON | GIE | PEIE | T0IE | INTE | RBIE | T0IF | INTF | RBIF | 0000 000x |
18Ch | — | Unimplemented | — | |||||||
18Dh | — | Unimplemented | — | |||||||
18Eh | — | Unimplemented | — | |||||||
18Fh | — | Unimplemented | — | |||||||
190h | — | Unimplemented | — | |||||||
191h | — | Unimplemented | — | |||||||
192h | — | Unimplemented | — | |||||||
193h | — | Unimplemented | — | |||||||
194h | — | Unimplemented | — | |||||||
195h | — | Unimplemented | — | |||||||
196h | — | Unimplemented | — | |||||||
197h | — | Unimplemented | — | |||||||
198h | — | Unimplemented | — | |||||||
199h | — | Unimplemented | — | |||||||
19Ah | — | Unimplemented | — | |||||||
19Bh | — | Unimplemented | — | |||||||
19Ch | — | Unimplemented | — | |||||||
19Dh | — | Unimplemented | — | |||||||
19Eh | — | Unimplemented | — | |||||||
19Fh | — | Unimplemented | — |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|
0x03, 0x83, 0x103, 0x183 | IRP | RP1 | RP0 | TO | PD | Z | DC | C |
Read/Write | R/W | R/W | R/W | R | R | R/W | R/W | R/W |
Initial Value | 0 | 0 | 0 | 1 | 1 | x | x | x |
RP1 | RP0 | BANK | Adresse |
---|---|---|---|
0 | 0 | 0 | 0x00 à 0x7F |
0 | 1 | 1 | 0x80 à 0xFF |
1 | 0 | 2 | 0x100 à 0x17F |
1 | 1 | 3 | 0x180 à 0x1FF |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|
0x81-0x181 | RBPU | INTEDG | T0CS | T0SE | PSA | PS2 | PS1 | PS0 |
Read/Write | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
Initial Value | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
PS2 | PS1 | PS0 | Diviseur TMR0 | Diviseur WDT |
---|---|---|---|---|
0 | 0 | 0 | 1:2 | 1:1 |
0 | 0 | 1 | 1:4 | 1:2 |
0 | 1 | 0 | 1:8 | 1:4 |
0 | 1 | 1 | 1:16 | 1:8 |
1 | 0 | 0 | 1:32 | 1:16 |
1 | 0 | 1 | 1:64 | 1:32 |
1 | 1 | 0 | 1:128 | 1:64 |
1 | 1 | 1 | 1:256 | 1:128 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|
0x0B, 0x8B, 0x10B, 0x18B | GIE | PEIE | T0IE | INTE | RBIE | T0IF | INTF | RBIF |
Read/Write | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
Initial Value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | x |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|
0x8E | - | - | - | - | OSCF | - | POR | BOR |
Read/Write | R | R | R | R | R/W | R | R/W | R/W |
Initial Value | 0 | 0 | 0 | 0 | 1 | 0 | 0 | x |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|
0x1F | C2OUT | C1OUT | C2INV | C1INV | CIS | CM2 | CM1 | CM0 |
Read/Write | R | R | R/W | R/W | R/W | R/W | R/W | R/W |
Initial Value | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |
CLRF PORTA ;Initialiser PORTA en réglant les bits en sortie MOVLW 0x07 ;Désactiver les comparateurs et MOVWF CMCON ;activer les broches pour les fonctions d'E/S sans inversion BCF STATUS, RP1 ;RP1=0 BSF STATUS, RP0 ;RP0=1 ->BANK1 MOVLW 0x1F ;Valeur utilisée pour initialiser la direction des données MOVWF TRISA ;Définissez RA <4: 0> comme entrée TRISA <5> toujours comme «1». ;TRISA <7: 6> dépend du mode de l’oscillateur
Opérande | Descriptions | Nombre de cycles | Registres impactés | |
---|---|---|---|---|
ADDWF | f,d | Somme W et f | 1 | C,DC,Z |
ANDWF | f,d | Et logique de W et f | 1 | Z |
CLRF | f | Efface f | 1 | Z |
CLRW | Efface W | 1 | Z | |
COMF | f,d | Complément à 2 de f | 1 | Z |
DECF | f,d | Décrémente f | 1 | Z |
DECFSZ | f,d | Décrémente f et saute si le résultat est 0 | 1 (2) | |
INCF | f,d | Incrémente f | 1 | Z |
INCFSZ | f,d | Incrémente f et saute si le résultat est 0 | 1 (2) | |
IORWF | f,d | Ou logique entre W et f | 1 | Z |
MOVF | f,d | Placer dans f | 1 | |
MOVWF | f,/td> | Placer W dans f | 1 | |
NOP | Instruction vide | 1 | Z | |
RLF | f,d | Rotation de bit à gauche avec injection dans la retenue | 1 | C |
RRF | f,d | Rotation de bit à droite avec injection dans la retenue | 1 | C |
SUBWF | f,d | Soustrait W de f | 1 | C,DC,Z |
SWAPF | f,d | Inversion des 4 bits haut et bas | 1 | |
XORWF | f,d | OU exclusif logique entre W et f | 1 | Z |
BCF | f,d | Efface un bit dans f | 1 | |
BSF | f,d | Place un bit dans f | 1 | |
BTFSC | f,d | Vérifie l'état d'un bit dans f et saute s'il est nulle | 1 (2) | |
BTFSS | f,d | Vérifie l'état d'un bit dans f et saute s'il est 1 | 1 (2) | |
ADDLW | K | Ajoute une valeur littérale à W | 1 | C,DC,Z |
ANDLW | K | Et logique d'une valeur littérale avec W | 1 | Z |
CALL | K | Appelle une sous fonction | 2 | |
CLRWDT | Efface le chien de garde | 1 | TO,PD | |
GOTO | K | Aller à l'adresse du programme | 2 | |
IORLW | K | Ou logique d'une valeur littérale et W | 1 | Z |
MOVLW | K | Placer une valeur littérale dans W | 1 | |
RETFIE | Retour d'une interruption | 2 | ||
RETLW | K | Retourne une valeur littérale dans W | 2 | |
RETURN | Retour d'une sous fonction | 2 | ||
SLEEP | Entre dans le mode stand bye, s'endort | 1 | TO,PD | |
SUBLW | K | Soustrait W d'une valeur littérale | 1 | C,DC,Z |
XORLW | K | Ou exclusif logique d'une valeur littérale et W | 1 | Z |
BCF STATUS, RP1 BSF STATUS, RP0 ;RP1=0 RP0=1 ->BANK1 BSF EECON1, WREN ;Enable write WREN=1 Permet les cycles d'écriture BCF INTCON, GIE ;Disable INTs. GIE: Global Interrupt Enable bit, 0 = Disables all interrupts BTFSC INTCON,GIE ;Vérifie l'état du bit GIE dans INTCON et saute s'il est nulle GOTO $-2 ;sinon recommence MOVLW 55h ; MOVWF EECON2 ;Write 55h EECON2=0x55 MOVLW AAh ; MOVWF EECON2 ;Write AAh EECON2=0xAA BSF EECON1,WR ;Set WR bit ;begin write BSF INTCON, GIE ;Enable INTs. BCF EECON1, WREN ;Disable write
BCF STATUS, RP1 BSF STATUS, RP0 ;RP1=0 RP0=1 ->BANK1 MOVLW DATA_EE_ADDR ;W=DATA_EE_ADDR MOVWF EEADR ;Address to read BSF EECON1, RD ;EE Read MOVF EEDATA, W ;EEDATA=W BCF STATUS, RP0 ;RP1=0 RP0=0 ->BANK0
INCLUDEcblock 0x20 char0 COUNT1 COUNT2 endc ORG 0x00 goto init init bsf STATUS, RP0 ;bank 1 ;---CONFIGURE SPBRG FOR DESIRED BAUD RATE movlw D'25' ;baud rate = 9600bps movwf SPBRG ;at 4MHZ ;---CONFIGURE TXSTA movlw B'00100100' movwf TXSTA ;Configures TXSTA as 8 bit transmission, transmit enabled, async mode, high speed baud rate bcf STATUS, RP0 ;bank 0 movlw B'10000000' movwf RCSTA ;enable serial port receive movlw 0x41 movwf char0 ;put A (ascii code 0x41) character to char0 register main movf char0, W movwf TXREG ;place the A character to TXREG goto wthere goto main wthere btfss TXSTA, TRMT ;check if TRMT is empty goto wthere ;if not, check again bcf STATUS, RP0 ;bank 0, if TRMT is empty then the character has been sent return end
INCLUDEorg 0x00 goto start start bsf STATUS, RP0 movlw .103 ;baud rate = 9600bps at 4MHZ movwf SPBRG movlw 0x24 movwf TXSTA clrf TRISB bcf STATUS, RP0 movlw 0x90 movwf RCSTA main btfss PIR1, RCIF goto main movf RCREG, W movwf PORTB goto main
PROCESSOR '16F876A' INCLUDE__CONFIG _XT_OSC & _WDT_OFF & _PWRTE_OFF & _CP_OFF & _LVP_OFF & _BODEN_OFF CBLOCK 0x20 D1 D2 FADE_STATE ;IF = 0x00 INCREMENT CCPR1L ELSE DECREMENT CCPR1L ENDC ORG 0x0000 INIT: ;PWM PERIOD = [(PR2)+1] * 4 * TOSC * (TMR2 PRESCALE VALUE) ;PR2 = TMR2 PERIOD REGISTER, TOSC = PIC CLOCK PERIOD (FOSC = 1 / TOSC) ;PWM DUTY CYCLE = (CCPR1L:CCP1CON<5:4>) * TOSC * (TMR2 PRESCALE VALUE) ;;;SET PWM FREQUENCY;;; BSF STATUS, RP0 ;SELECT BANK 01 MOVLW D'128' ;SET PR2 TO 128 DECIMAL SO THE PWM PERIOD = 2064uS => PWM FREQUENCY = 484Hz MOVWF PR2 ;PR2=128 BCF STATUS, RP0 ;SELECT BANK 00 ;;;SET PWM STARTING DUTY CYCLE;;; CLRF CCPR1L MOVLW B'00001100' ;SET PWM MODE, BITS 5 AND 4 ARE THE TWO LSBs OF THE 10BIT DUTY CYCLE REGISTER (CCPR1L:CCP1CON<5:4>) MOVWF CCP1CON ;;;SET PWM PIN TO OUTPUT MODE;;; BSF STATUS, RP0 ;SELECT BANK 01 BCF TRISC, 2 ;SET RC2 AS OUTPUT, TO USE FOR PWM BCF STATUS, RP0 ;SELECT BANK 00 ;;;SET TIMER 2 PRESCALE VALUE;;; ;PRESCALE = 16 SO THE PWM PERIOD = 2064uS => PWM FREQUENCY = 484Hz MOVLW B'00000010' MOVWF T2CON ;;;CLEAR TIMER 2 MODULE;;; CLRF TMR2 ;;;ENABLE TIMER 2 MODULE;;; BSF T2CON, TMR2ON CLRF FADE_STATE MAIN: CALL DELAY MOVLW 0x00 IORWF FADE_STATE, W BTFSS STATUS, Z ;IF FADE_STATE == 0 GOTO INC_CCPR1L GOTO DEC_CCPR1L ;ELSE GOTO DEC_CCPR1L INC_CCPR1L: INCFSZ CCPR1L ;INCREMENT CCPR1L GOTO MAIN GOTO CHANGE_STATE_0 ;IF WE HAVE AN OVERFLOW GOTO CHANGE_STATE DEC_CCPR1L: DECFSZ CCPR1L ;DECREMENT CCPR1L GOTO MAIN ;IF WE HAVE AN OVERFLOW GOTO CHANGE_STATE CHANGE_STATE: COMF FADE_STATE, F ;TOGLE FADE_STATE BITS INCFSZ CCPR1L GOTO MAIN CHANGE_STATE_0: COMF FADE_STATE, F ;TOGLE FADE_STATE BITS DECFSZ CCPR1L GOTO MAIN DELAY ;9993 CYCLES MOVLW 0xCE ; 1 cy MOVWF D1 ;D1=0xCE .206 1 cy MOVLW 0x08 ; 1 cy MOVWF D2 ;D2=0x08 1 cy DELAY_0 DECFSZ D1, F ;Décrémente D1 et saute si le résultat est 0, 1 cycle si non, 2 si oui GOTO $ + 2 ;sinon boucle en 4 cycles 0xCE 207*5+4=1039 DECFSZ D2, F ;Décrémente D2 et saute si le résultat est 0, 1 cycle si non, 2 si oui GOTO DELAY_0 ;sinon boucle en 2 cycles (1039+3)*9=9378 ;3 CYCLES GOTO $ + 1 NOP ;4 CYCLES (INCLUDING CALL) RETURN END